This application claims priority under 35 USC §119 to Korean Patent Application No. 2006-84910, filed on Sep. 5, 2006 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
1. Field of the Invention
The present invention relates generally to correlated double sampling (CDS) and analog-to-digital conversion (ADC), and more particularly to concurrent CDS and ADC such as in an image sensor for increased frequency performance.
2. Background of the Invention
Correlated double sampling (CDS) is widely used to detect only a desired signal component in a device such as an image sensor by removing, for example, fixed pattern noise (FPN), from a signal output from a unit pixel. For CDS, a difference between a reset signal and an image signal is determined. The reset signal is generated with a predetermined voltage level applied on the unit pixel. The image signal represents an intensity of light sensed by the unit pixel. Thus, CDS is effective in reducing FPN that is inherent in the unit pixels and also noise caused by characteristic differences between the unit pixels.
FIG. 1 is a block diagram of a conventional unit block 1 in a conventional CMOS (complementary metal oxide semiconductor) image sensor, for performing CDS and analog-to-digital conversion (ADC) sequentially in series. Referring to FIG. 1, the unit block 1 includes a pixel 10 and a unit CDS block 13. For clarity of description, an image signal processor (ISP) 19 is illustrated together with the unit block 1. A pixel array of the CMOS image sensor includes a plurality of pixels and a CDS array having a plurality of unit CDS blocks, each having similar components to the unit CDS block 13.
The pixel 10 includes a sensor (e.g., a photodiode) for detecting an intensity of light by photoelectric conversion and a photoelectric converter (e.g., four transistors) for outputting an electrical image signal A(S) from such photoelectric conversion and a reset signal A(R) from an applied reset voltage, both as analog signals.
The unit CDS block 13 includes a CDS circuit 15 for generating a difference A(R-S) between the reset signal A(R) and the image signal A(S) from the pixel 10 using CDS. In addition, the unit CDS block 13 includes an ADC unit 17 for converting the difference signal A(R-S) that is an analog signal from the CDS circuit 15 into a digital signal D(R-S). The ISP 19 performs diverse signal processing operations on the digital signal D(R-S) from the ADC unit 17.
The unit CDS block 13 performs CDS and ADC successively with continuously performing the ADC after performing the CDS or with performing the ADC a predetermined period of time after performing the CDS. Here, it is assumed that the unit CDS block 13 continuously performs the CDS and the ADC in succession.
FIG. 2 is a timing diagram of signals when the unit CDS block 13 of FIG. 1 performs CDS and ADC. Referring to FIG. 2, analog reset and images signals are sampled and output from the pixel 10 in units of each line (i.e. row) in a sequential scanning manner as a respective unit CDS block 13 is coupled to each column of pixels. In FIG. 2, a scan time “1H Time” indicates the time allowed for completing CDS and ADC with respect to a single line (i.e., row).
During time TCDS when the CDS is performed, reset signal sampling and image signal sampling are sequentially performed. Such a time TCDS determines operating speed and other characteristics of the CMOS image sensor. Thus, the time TCDS should be maintained independently and absolutely. Time TADC during which the ADC is performed may be more flexibly maintained than the time TCDS. However, the time TADC also determines the operating frequency and limits a frame rate of the CMOS image sensor.